Cookies disallowed, click button to change.
Cookies allowed, click button to disallow.
OSP is a framework of algorithms for putting disparate sensors and microprocessors from different manufacturers together to enable them to work together on complex tasks, such as contextual, sensing, pedestrian dead reckoning (PDR), in low power."
OSP to source code will be released on Github under Apache License, Version 2.0.
4.8 release of the GNU Tools for ARM Embedded Processor includes updated version of the newlib-nano version 2.
Source code for the newlib-nano-2 is on github link https://github.com/32bitmicro/newlib-nano-2
There are 2 branches that correspond to the specific release:
Picture below shows ADC board plugged in the ZedBoard FMC connector, external power is provided from programmable power supply on the left, while input is driven from the signal generator on the right.
ZedBoard is a low cost development board for the dual Cortex-A9 + FPGA fabric programmable SoC from Xilinx.
The end is near!
"We have been hearing about the imminent demise of Moore's Law quite a lot recently. Most of these predictions have been targeting the 7nm node and 2020 as the end-point. But we need to recognize that, in fact, 28nm is actually the last node of Moore's Law."
To celebrate Raspberry Pi birthday Broadcom has published full documentation for the VideoCore IV GPU found on Rasberry Pi BCM2835 chip. In addition full open source driver has been released - click here for link to the announcement page.
However, open source work has been going on for quite some time and it "has the potential to unleash the full 24 GFLOPS power of the RaspberryPi for computation." See the videocoreiv-qpu at github - click here.
24 GFLOPS ~ 1$ per GFLOP is not a bad deal!
The VideoCore IV quad processor (QPU) is a SIMD machine with the following key features:
For all intents and purposes the QPU can be regarded as a 16-way 32-bit SIMD processor with an instruction cycle time of four system clocks. The latency of floating point ALU operations is accommodated within these four clock cycles, giving single cycle operation from the programmer’s perspective. Internally the QPU is a 4-way SIMD processor multiplexed to 16-ways by executing the same instruction for four clock cycles on four different 4-way vectors termed ‘quads’. This allows a simple and efficient pipeline design without complex interlocks and forwarding paths, which is well matched to processing a stream of pixel quads. The four clock instruction cycle also allows four QPUs to be clustered together to share a common instruction cache, forming what is termed a processing ‘slice’. The QPU ALU is dual-issue, the design uses a small number of accumulators in conjunction with large single- ported register files to provide the bandwidth needed to perform two binary operations per cycle. Floating-point reciprocal, reciprocal square root, logarithm, and exponentiation operations are performed by a separate, shared block in each slice.
Machinoid is optimized for the machines with built-in hard real-time support targeting applications in Robotics, CNC and 3D Printing.
- hard real-time support
- headless operation
Raspberry Pi goals are:
- support for embedded hardware including LCDs, I2C and SPI devices etc.
- compatibility with Raspbian distribution
Current 2013-7-8 image is available for download on this page click here!
It is based on Linux kernel 3.5.7 and Xenomai 22.214.171.124 Installation instructions are on the same page.
Raspberry Pi Forum thread link
"Productive programming of modern embedded systems is a challenge. For example, consider a smart phone that is using multiple processor cores of multiple capabilities. The functionalities of these cores vary dynamically based on the application requirements; different cores are running on different OSes.
One of the OSes might be handling user interface plus file and data management and the other core, invisible to the user, might be managing low-level activities such as connecting and handling calls. It is a complicated task for a single OS to track and manage all resources and operations, hence the need for more than one OS. How to enable communication between cores, share resources, and synchronize accesses? Some other complicated programming questions include:
1. Can conventional thread creation and management techniques that were originally developed for general purpose processors be used for embedded platforms? Hint: Resource is scarce in embedded systems - the maximum number of cores available on an embedded platform is presently 64.
2. What are the challenges that embedded platforms pose with regard to memory accesses? Hint: Embedded systems contain multiple memory spaces that are dedicated to each core. These memories maintain a distinct address space that are not accessible from other threads.
3. Can conventional, general purpose synchronization be used for embedded systems as well? Hint: Embedded systems, especially heterogeneous ones, are asymmetric multiprocessor (AMP)-based architectures; processors are loosely coupled, with each processor having its own OS and memory. "
"A bootloader resides in protected program memory on a given microcontroller. It is usually the first software to run after power up or reset and is highly processor- and board-specific. The bootloader could be considered a “dumb” piece of code in that it doesn’t understand what application needs to be performed or even what the device function is. Rather, it is specially designed to understand communication from the outside world via any number of communication protocols (UART, I2C, SPI, CAN, Ethernet) and to understand the memory map of the microcontroller. When the bootloader does its job, it communicates with the outside world, or host, reads the data file sent by the host, and updates the Microprocessor in which it resides to run the new application code provided. "