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CoAP - open source implementations in C


libcoap: - click here

C-Implementation of CoAP

microcoap - click here

A small CoAP implementation for microcontrollers

smcp - click here

A flexible CoAP stack for embedded devices and computers. draft-ietf-core-coap-13 compatible.


DIY guide to building multiprotocol IoT web based application server

Typical Internet of Things (IoT) application requires supporting multiple protocols to route the data from and to the local sensor nodes by the internet and web enabled application server.

This article explains in detail architecture of the web based application server.

The Connected World Awaits - click here

"How It Works

In IoT applications, the device to be monitored or controlled has an embedded wireless transceiver that talks to a gateway or router that has an Internet connection (Fig. 1). For example, a home thermostat would communicate by Wi-Fi with the home Wi-Fi router that connects to the Internet via a cable TV link. That link connects with a remote cloud-based server that supplies the application’s intelligence, collects the data, analyzes it, stores it, makes decisions, and initiates actions. This server connects by way of the Internet to the applications interface, where another machine like a PC analyzes and displays status and actions. Smartphones are popular interfaces, and they’re quickly becoming our all-purpose remote control."


Raspberry Pi

Tutorial: How to Set Up a Raspberry Pi Web Server - click here


RT5350 based devices

 Mini USB Portable 3G/4G router - rt5350f  - click here

 Step by step guide to setting up RT5350 based  HAME A5 Mini and HAME A15 portable routers with OpenWRT firmware and bootloader, links to binary images.  Contains description of GPIO, connecting UART, programming SPI Flash and hardware modifications to increase memory.


 SoftEther VPN Project - click here

"An Open-Source Free Cross-platform Multi-protocol VPN Program,
as an academic project from University of Tsukuba"

 How to Setup a Multi-Protocol VPN Server Using SoftEther - click here

"This article explains how to install and configure a multi-protocol VPN server using the SoftEther package. We enable and configure OpenVPN and L2TP over IPSec and SSTP VPN Servers on Linux."


Routing serial RS232 protocol over the internet

Serial port to network proxy: ser2net  - click here

Raspberry Pi + ser2net = Cheap NM16A (Serial Console Server) - click here

Serial Over IP: serialoverip - click here

Sercd plus xinetd - click here

"RFC 2217-compliant serial port redirector. It lets you share a serial port through a network. It is based on sredird."

RFC 2217 Telnet Com Port Control Option - click here

Open Sensor Platform endorsed by ARM

Sensor hubs made easy.

"OSP is a framework of algorithms for putting disparate sensors and microprocessors from different manufacturers together to enable them to work together on complex tasks, such as contextual, sensing, pedestrian dead reckoning (PDR), in low power."

OSP to source code will be released on Github under Apache License, Version 2.0.

Click here for link



4.8 release of the GNU Tools for ARM Embedded Processor includes updated version of the newlib-nano version 2.

Source code for the newlib-nano-2 is on github link

There are 2 branches that correspond to the specific release:

  • newlib-nano-2.1 - corresponds to gcc-arm-none-eabi-4_8-2014q1-20140314
  • newlib-nano-2.0 - corresponds to gcc-arm-none-eabi-4_8-2013q4-20131204

ZedBoard with High Speed Single Channel 12-bit ADC Board

ADC-FMC-141 is a high speed (up to 500 MSPS single channel) ADC convert board which can be used the Xilinx Zynq®-7000 based ZedBoard.

Picture below shows ADC board plugged in the ZedBoard FMC connector, external power is provided from programmable power supply on the left, while input is driven from the signal generator on the right.


ZedBoard is a low cost development board for the dual Cortex-A9 + FPGA fabric programmable SoC from Xilinx.


28nm – The Last Node of Moore's Law

The end is near!

"We have been hearing about the imminent demise of Moore's Law quite a lot recently. Most of these predictions have been targeting the 7nm node and 2020 as the end-point. But we need to recognize that, in fact, 28nm is actually the last node of Moore's Law."

Click here to link

Broadcom publishes full documentation for VideoCore® IV QPU

To celebrate Raspberry Pi birthday Broadcom has published full documentation for the VideoCore IV GPU found on Rasberry Pi  BCM2835 chip. In addition full open source driver has been released - click here for link to the announcement page.

 However, open source work has been going on for quite some time and it "has the potential to unleash the full 24 GFLOPS power of the RaspberryPi for computation." See the videocoreiv-qpu at github - click here.

 24 GFLOPS ~ 1$ per GFLOP is not a bad deal!

The VideoCore IV quad processor (QPU) is a SIMD machine with the following key features:

  • A highly uniform 64-bit instruction encoding
  • Four-way physical parallelism
  • 16-way virtual parallelism (4-way multiplexed over four successive clock cycles)
  • A dual-issue floating-point ALU (one add and multiply per cycle)
  • Two large single-ported register files • Five accumulators • I/O mapped into the register space
  • Support for two hardware threads
  • Instruction and register level coupling to the 3D hardware

For all intents and purposes the QPU can be regarded as a 16-way 32-bit SIMD processor with an instruction cycle time of four system clocks. The latency of floating point ALU operations is accommodated within these four clock cycles, giving single cycle operation from the programmer’s perspective. Internally the QPU is a 4-way SIMD processor multiplexed to 16-ways by executing the same instruction for four clock cycles on four different 4-way vectors termed ‘quads’. This allows a simple and efficient pipeline design without complex interlocks and forwarding paths, which is well matched to processing a stream of pixel quads. The four clock instruction cycle also allows four QPUs to be clustered together to share a common instruction cache, forming what is termed a processing ‘slice’. The QPU ALU is dual-issue, the design uses a small number of accumulators in conjunction with large single- ported register files to provide the bandwidth needed to perform two binary operations per cycle. Floating-point reciprocal, reciprocal square root, logarithm, and exponentiation operations are performed by a separate, shared block in each slice.

Machinoid hard real-time distribution optimized for machines

Machinoid is optimized for the machines with built-in hard real-time support targeting applications in Robotics, CNC and 3D Printing.

Goals are:
- stability
- hard real-time support
- headless operation

Raspberry Pi goals are:
- support for embedded hardware including LCDs, I2C and SPI devices etc.
- compatibility with Raspbian distribution

Current 2013-7-8 image is available for download on this page click here!
It is based on Linux kernel 3.5.7 and Xenomai Installation instructions are on the same page.

Raspberry Pi Forum thread link


A portable OpenMP runtime library based on MCAPI/MRAPI

"Productive programming of modern embedded systems is a challenge. For example, consider a smart phone that is using multiple processor cores of multiple capabilities. The functionalities of these cores vary dynamically based on the application requirements; different cores are running on different OSes. 

One of the OSes might be handling user interface plus file and data management and the other core, invisible to the user, might be managing low-level activities such as connecting and handling calls. It is a complicated task for a single OS to track and manage all resources and operations, hence the need for more than one OS. How to enable communication between cores, share resources, and synchronize accesses? Some other complicated programming questions include: 

1. Can conventional thread creation and management techniques that were originally developed for general purpose processors be used for embedded platforms? Hint: Resource is scarce in embedded systems - the maximum number of cores available on an embedded platform is presently 64. 

2. What are the challenges that embedded platforms pose with regard to memory accesses? Hint: Embedded systems contain multiple memory spaces that are dedicated to each core. These memories maintain a distinct address space that are not accessible from other threads. 

3. Can conventional, general purpose synchronization be used for embedded systems as well? Hint: Embedded systems, especially heterogeneous ones, are asymmetric multiprocessor (AMP)-based architectures; processors are loosely coupled, with each processor having its own OS and memory. "


Web page link

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