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"I am sure many of you will be familiar with Donald Knuth’s oft-quoted sentiment:
“We should forget about small efficiencies, say about 97% of the time: premature optimization is the root of all evil.”
How many of you have seen the second sentence?
“Yet we should not pass up our opportunities in that critical 3%.”
Both parts are important. We all realize that optimization is a valuable activity but it only reaches maximum payback for minimum effort when we apply the available effort carefully in exactly the right place."
"Cache coherency ensures that each core operates on the most up-to-date data, whether it resides in its cache, another core's cache, or main memory. That sounds simple but it is actually hard when you have multiple cores working in parallel and continually updating their cache contents. In the past, software running on the cores has been used to keep cache contents up to date. However, since this is a comparatively slow activity that drains power, it is best performed in hardware.
In order to support a standard way of implementing cache coherent systems, ARM published the AXI Coherency Extensions (ACE) specification in 2011 to add to their set of AMBA protocols. ARM also released the CCI-400 interconnect IP which provides a cache coherent interconnect to link the components in a mobile SoC. It is these key building blocks, the ACE specification and CCI-400 interconnect (which tie together cores such as the A7 or A15) that enable multicore cache coherent systems. However, they also present new challengers for verification engineers who must ensure that the mobile SoCs will function correctly."
"Thanks to some recent work, mainly by Stefano Stabellini, we are now able to start our first guest domain, including paravirtual console disk and network devices!
The main implementation work here has been to implement support for the core pieces of infrastructure will underpins the PV drivers, primarily that is event channels and grant tables all of which Stefano has implemented recently. One of our key design goals with this port of Xen was to make good use of the hardware virtualisation extensions, and at the same time implement paravirtualisation where it offers obvious benefits. For example we wanted to use paravirtualised device drivers for I/O as they provide significant performance benefits compared to emulated devices."
"While only an “update” for the Java community, this release is a significant milestone not only for Calxeda, but the entire ARM ecosystem. Java SE 7 Update 6 now introduces a general-purpose port of the JDK to Linux ARM. "
Oracle releases JDK for Linux ARM, JRE for Mac OS X - blog page link
"With JDK 7u6 we are also adding a general-purpose port of the JDK (but not a desktop JRE) to Linux ARM, and making it available under the same licensing terms as Oracle Java for other platforms. This JDK release is aimed at the emerging ARM server market, and for the community working on development boards such as the BeagleBoard, PandaBoard and the Raspberry Pi. This port provides 32-bit binary for ARMv6 and v7, with full support for Swing/AWT, both client (C1) and server (C2) compilers and runs on most Linux distributions. One caveat is that the current binary is softfloat ABI only, so it won't work with (for example) the Raspbian distribution which uses the hardfloat ABI. We are planning to add hardfloat support in an upcoming JDK release, as well as support for JavaFX on ARM."
Oracle Press Release - web page link
"Starting with the ARMv7 architecture and the first Cortex CPU based on it, the A8, we already began to think of these devices as superphones or mini-computers once the 1 GHz barrier was broken. Then came the dual core Cortex A9 chips and, with them, brought a browsing experience with rich graphics similar to what was available on PC's just 6 or 7 years before that, which is still very impressive when you consider it's all done on a mobile phone.
Fast forward to today, and we now have quad core Cortex A9 processors, and more. Despite this, I think many of us are already looking forward to the inevitable launch of chips based on the new Cortex A15 CPU, that promises to get ever closer to a level of performance that is good for laptops. this, all the while maintaining a low-power profile. So what can we expect from this next-gen chip compared to the Cortex A9 we're using now?"
"Page colouring is a technique for allocating pages for an MMU such that the pages exist in the cache in a particular order. The technique is sometimes used as an optimization (and is not specific to ARM), but as a result of the cache architecture some ARMv6 processors actually require that the allocator uses some page colouring. Some ARMv7 processors also have related (though much less severe) restrictions. This article will explain why the cache architecture imposes this restriction, and what it means in practice."