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Register Access in C++

"Embedded programmers traditionally use C as their language of choice. And why not? It's lean and efficient, and lets you get as close to the metal as you want. Of course C++, used properly, provides the same level of efficiency as the best C code. Moreover, you can also leverage powerful C++ features to write cleaner, safer, more elegant low-level code. In this article, I present a C++ scheme for accessing hardware registers in an optimal way."

Read more web page link

"Remembering the memories"

"A trip down memory lane reveals more about how memory radically changed the nature of digital electronics."

...

Web page link

"What Every Programmer Should Know About Memory"

Published 2007

Abstract

As CPU cores become both faster and more numerous, the limiting factor for most programs is
now, and will be for some time, memory access. Hardware designers have come up with ever
more sophisticated memory handling and acceleration techniques–such as CPU caches–but
these cannot work optimally without some help from the programmer. Unfortunately, neither
the structure nor the cost of using the memory subsystem of a computer or the caches on CPUs
is well understood by most programmers. This paper explains the structure of memory subsystems
in use on modern commodity hardware, illustrating why CPU caches were developed, how
they work, and what programs should do to achieve optimal performance by utilizing them.

"As CPU cores become both faster and more numerous, the limiting factor for most programs is now, and will be for some time, memory access. Hardware designers have come up with ever more sophisticated memory handling and acceleration techniques–such as CPU caches–but these cannot work optimally without some help from the programmer. Unfortunately, neither the structure nor the cost of using the memory subsystem of a computer or the caches on CPUs is well understood by most programmers. This paper explains the structure of memory subsystems in use on modern commodity hardware, illustrating why CPU caches were developed, how they work, and what programs should do to achieve optimal performance by utilizing them."

PDF document link

 

"Variations on a flexible array theme"

"Different dialects of C and C++ support different forms of flexible array members. Unfortunately, the more expressive forms are the less portable ones."

...

Web page link

"Implement an MP3 audio decoder with the ARM Neon Multimedia extensions"

"The ARM Cortex-A8 processor is the most advanced, high performance, low-power processor by ARM. Based on the ARMv7 architecture, the processor suits a variety of mobile and consumer applications, including mobile phones, STBs, game consoles and car navigation. As the core technology of Cortex-A8 processor,

NEON technology has the flexibility to implement multiple combinations of video encode/decode, 3D graphics, speech processing, audio decoding, image processing and baseband processing."

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Web page link

Collection of articles from Planet Analog in the form of a dialogue discussing power supply design including grounding, decoupling and bypass-capacitors.

 

"A bypass-capacitor dialogue peels back the layers" series

Part 1: "A bypass-capacitor dialogue peels back the layers" web page link

Basic information about bypass-capacitors, model, definition, practical discussion of selecting, ESL and ESR.

Part 2: "Part 2: The theory of ground relativity" - web page link

Discussion of the ground plane design, cuts, trace widths, coupling, via inductance, ground loops. 

Part3: "Continuing the discussion on layout considerations" - web page link

 

"The elegance of ferrite beads" - web page link

Detailed discussion of the ferrite beads, model, frequency response.

 

"Choosing and Using Bypass Capacitors"

Part 1: "Choosing and Using Bypass Capacitors"- web page link

Part 2: "Common Types of Capacitors and Trade-offs"- web page link

Part 3: "Bypass Capacitor Application Examples" - web page link

 

Nokia has posted 'User Interface Concept Proposal' for the next release of  Symbian^4 mobile OS.

Senak peak page with video and downloadable presentation

Wiki page link

Forum page link has link to PDF version of the presenation

"Deterministic dynamic memory allocation & fragmentation in C & C++"

Published January 2010

In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. 

However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issue is not an option.

Dynamic memory allocation tends to be non-deterministic; the time taken to allocate memory may not be predictable and the memory pool may become fragmented, resulting in unexpected allocation failures. This article details the problems and an approach to deterministic dynamic memory allocation.

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"Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines"

Abstract:

This document defines the power delivery feature set necessary to support Intel
processors’ Vcc power delivery requirements for desktop computer systems using the
LGA775 socket. This includes design recommendations for DC to DC regulators, which
convert the input supply voltage to a processor consumable Vcc voltage along with
specific feature set implementation such as thermal monitoring and dynamic voltage
identification.

This document defines the power delivery feature set necessary to support Intel processors’ Vcc power delivery requirements for desktop computer systems using the LGA775 socket. This includes design recommendations for DC to DC regulators, which convert the input supply voltage to a processor consumable Vcc voltage along with specific feature set implementation such as thermal monitoring and dynamic voltage identification.

PDF document link

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