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"Cache coherency ensures that each core operates on the most up-to-date data, whether it resides in its cache, another core's cache, or main memory. That sounds simple but it is actually hard when you have multiple cores working in parallel and continually updating their cache contents. In the past, software running on the cores has been used to keep cache contents up to date. However, since this is a comparatively slow activity that drains power, it is best performed in hardware.
In order to support a standard way of implementing cache coherent systems, ARM published the AXI Coherency Extensions (ACE) specification in 2011 to add to their set of AMBA protocols. ARM also released the CCI-400 interconnect IP which provides a cache coherent interconnect to link the components in a mobile SoC. It is these key building blocks, the ACE specification and CCI-400 interconnect (which tie together cores such as the A7 or A15) that enable multicore cache coherent systems. However, they also present new challengers for verification engineers who must ensure that the mobile SoCs will function correctly."
It was bound to happen that we would have the first chip project on the Kickstarter but the Parallella Computing Platform comes with a bang. It is based on Xillinx ZYNQ-7000 FPGA with dual core Cortex-A9 and Adapteva chip with 16 to 64 floating point Epiphany cores. Current system is prototyped on a Xillinx Zedboard.
Looks like Atmel is back in the game of Cortex-M4 world domination with the release of SAM4L family.
However, they might have spent a bit more time thinking about the terminology. Here are couple of our suggestions: "The Peripheral Event System" call it PESky, picoPower let''s not be shy about is picoPOWER! SleepWalking we simply give up on this one, why would anyone wanted to use MCU which is sleepwalking!? To illustrate the point we will use selective quote technique, because it is "eliminating unneeded, power-consuming CPU", not a bad idea, PESky peripherals rule! And finally the family name, c'mon why pass on such a grand opportunity to use the number 4, call it SAM4YOU or SAM4ALLOFUS.
Terminology notwithstanding the tech in this chip looks very promising.
Press release web page link
"The Peripheral Event System is a real-time network that allows peripherals to communicate directly with one another without using the central processing unit (CPU). In addition, SleepWalking technology allows a peripheral to qualify and evaluate incoming data without the use of the CPU, eliminating unneeded, power-consuming CPU wake-ups to conserve power. This allows the peripherals to qualify an event and decide to wake-up whether it is from capacitive touch, I2C address match or an ADC threshold. The SAM4L devices feature peripherals designed to reduce the overall power consumption such as the innovative LCD controller that include ASCII character mapping, hardware scrolling and blinking support. "